module P302703A

title 'Display Board'


declarations
DCK pin 39; "Data Clock 40 MHz"
DBC pin 50 istype 'reg'; "Display Board Code"
MRC pin 44; "Message Router Code"
MDC pin 47; "Message Detector Code"
ARCK pin 49; "Asynchronous Reference Clock 32.768 kHz."
!RST pin 48 istype 'com'; "Hardware Reset"
!RSTSW pin 78; "Reset Switch"
!SHSET pin 29; "Show Set"
!CHSET pin 30; "Change Set"
!LUP pin 72 istype 'com'; "Upload Lamp"
!LEY pin 53 istype 'com'; "Empty Lamp"
!LRST pin 70 istype 'com'; "Reset Lamp"
!DF1,!DF2 pin 28, 31 istype 'com'; "Display Flash Lamps"
LA1..LA8 pin 22,21,20,19,17,16,15,14 istype 'com'; "Antenna Lamps"
LC1..LC15 pin 100,99,97,94,92,86,84,3,4,5,6,8,9,10,11 istype 'com'; "Channel Lamps"
equations


declarations
RCK node istype 'reg';
equations

RCK.clk = DCK;
RCK := ARCK;

declarations
RESET node istype 'com';
equations


RST.oe = RSTSW;
RST = 1;
RESET = RST.pin;

declarations
MDCR0..MDCR3 node istype 'reg';
mdcr = [MDCR3..MDCR0];
CID0..CID3 node istype 'reg';
cid = [CID3..CID0];
MSEL0..MSEL2 node istype 'reg';
msel = [MSEL2..MSEL0];
FS1 node istype 'reg'; "Flash State"
equations

mdcr.clk = DCK;
mdcr.aclr = RESET;
when mdcr==0 then {
  when MDC then mdcr := 1 else mdcr := 0;
}
when (mdcr >= 1) & (mdcr <= 9) then {
  mdcr := mdcr + 1;
}
when (mdcr >= 10) then mdcr := 0;

FS1.clk = !DCK;
FS1 := (mdcr == 10);

cid.clk = DCK;
when mdcr==1 then CID3:=MDC else CID3:=CID3;
when mdcr==2 then CID2:=MDC else CID2:=CID2;
when mdcr==3 then CID1:=MDC else CID1:=CID1;
when mdcr==4 then CID0:=MDC else CID0:=CID0;

msel.clk = DCK;
when mdcr==6 then MSEL2:=MDC else MSEL2:=MSEL2;
when mdcr==7 then MSEL1:=MDC else MSEL1:=MSEL1;
when mdcr==8 then MSEL0:=MDC else MSEL0:=MSEL0;


declarations
indicator interface (CK, FLASH -> ON);
LAC1..LAC8 functional_block indicator;
LCC1..LCC15 functional_block indicator;
equations

LAC1.FLASH = FS1 & (msel == 0);
LAC1.CK = RCK;
LA1 = LAC1.ON;

LAC2.FLASH = FS1 & (msel == 1);
LAC2.CK = RCK;
LA2 = LAC2.ON;

LAC3.FLASH = FS1 & (msel == 2);
LAC3.CK = RCK;
LA3 = LAC3.ON;

LAC4.FLASH = FS1 & (msel == 3);
LAC4.CK = RCK;
LA4 = LAC4.ON;

LAC5.FLASH = FS1 & (msel == 4);
LAC5.CK = RCK;
LA5 = LAC5.ON;

LAC6.FLASH = FS1 & (msel == 5);
LAC6.CK = RCK;
LA6 = LAC6.ON;

LAC7.FLASH = FS1 & (msel == 6);
LAC7.CK = RCK;
LA7 = LAC7.ON;

LAC8.FLASH = FS1 & (msel == 7);
LAC8.CK = RCK;
LA8 = LAC8.ON;

LCC1.FLASH = FS1 & (cid == 1);
LCC1.CK = RCK;
LC1 = LCC1.ON;

LCC2.FLASH = FS1 & (cid == 2);
LCC2.CK = RCK;
LC2 = LCC2.ON;

LCC3.FLASH = FS1 & (cid == 3);
LCC3.CK = RCK;
LC3 = LCC3.ON;

LCC4.FLASH = FS1 & (cid == 4);
LCC4.CK = RCK;
LC4 = LCC4.ON;

LCC5.FLASH = FS1 & (cid == 5);
LCC5.CK = RCK;
LC5 = LCC5.ON;

LCC6.FLASH = FS1 & (cid == 6);
LCC6.CK = RCK;
LC6 = LCC6.ON;

LCC7.FLASH = FS1 & (cid == 7);
LCC7.CK = RCK;
LC7 = LCC7.ON;

LCC8.FLASH = FS1 & (cid == 8);
LCC8.CK = RCK;
LC8 = LCC8.ON;

LCC9.FLASH = FS1 & (cid == 9);
LCC9.CK = RCK;
LC9 = LCC9.ON;

LCC10.FLASH = FS1 & (cid == 10);
LCC10.CK = RCK;
LC10 = LCC10.ON;

LCC11.FLASH = FS1 & (cid == 11);
LCC11.CK = RCK;
LC11 = LCC11.ON;

LCC12.FLASH = FS1 & (cid == 12);
LCC12.CK = RCK;
LC12 = LCC12.ON;

LCC13.FLASH = FS1 & (cid == 13);
LCC13.CK = RCK;
LC13 = LCC13.ON;

LCC14.FLASH = FS1 & (cid == 14);
LCC14.CK = RCK;
LC14 = LCC14.ON;

LCC15.FLASH = FS1 & (cid == 15);
LCC15.CK = RCK;
LC15 = LCC15.ON;


declarations
MRCR0..MRCR2 node istype 'reg';
mrcr = [MRCR2..MRCR0];
FS2 node istype 'reg';
DS,AE node istype 'reg';
equations


mrcr.clk = DCK;
mrcr.aclr = RESET;
when mrcr==0 then {
  when MRC then mrcr := 1 else mrcr := 0;
}
when (mrcr >= 1) & (mrcr <= 9) then {
  mrcr := mrcr + 1;
}
when (mrcr >= 10) then mrcr := 0;

DS.clk = DCK;
when mrcr==1 then DS:=MRC else DS:=DS;

AE.clk = DCK;
when mrcr==2 then AE:=MRC else AE:=AE;



LRST = RST.pin;

declarations
UPC7..UPC0 node istype 'reg';
upc = [UPC7..UPC0];
equations

upc.clk = RCK;
upc.ap = DS;
when upc == 0 then upc := 0;
else upc := upc - 1;
LUP = upc > 0;

LEY = AE # RESET;

DF1 = SHSET;
DF2 = CHSET;

end