[Device]
Family = lc4k;
PartNumber = LC4064ZE-7MN64C;
Package = 64csBGA;
PartType = LC4064ZE;
Speed = -7.5;
Operating_condition = COM;
Status = Production;
EN_PinGLB = yes;
EN_PinMacrocell = yes;

[Revision]
Parent = lc4k64e.lci;
DATE = 03/06/2018;
TIME = 16:03:17;
Source_Format = ABEL_Schematic;
Synthesis = Synplify;

[Ignore Assignments]

[Clear Assignments]

[Backannotate Assignments]

[Global Constraints]

[Location Assignments]
layer = OFF;
CK = pin,F1,-,-,-;
F4 = pin,E1,-,-,-;
F3 = pin,D1,-,-,-;
F2 = pin,C1,-,-,-;
F1 = pin,B1,-,-,-;
F0 = pin,A1,-,-,-;
SHDN = pin,G8,-,-,-;
TP1 = pin,H2,-,-,-;
TP2 = pin,H3,-,-,-;
TP3 = pin,H4,-,-,-;
CONV = pin,C8,-,-,-;
SDO = pin,A6,-,-,-;
SCK = pin,A5,-,-,-;
SDI = pin,A7,-,-,-;
L0 = pin,A2,-,-,-;
L1 = pin,A3,-,-,-;
L2 = pin,B4,-,-,-;
L3 = pin,C4,-,-,-;
L4 = pin,E6,-,-,-;
L5 = pin,E7,-,-,-;
L6 = pin,E8,-,-,-;
L7 = pin,G1,-,-,-;
L8 = pin,G2,-,-,-;
L9 = pin,G3,-,-,-;
L10 = pin,G4,-,-,-;
L11 = pin,G5,-,-,-;
L12 = pin,F5,-,-,-;

[Group Assignments]
layer = OFF;

[Resource Reservations]
layer = OFF;

[Fitter Report Format]

[Power]

[Source Constraint Option]

[Fast Bypass]

[OSM Bypass]

[Input Registers]
NONE = CK, SDO, L0, L1, L2, L3, L4, L5, L6, L7, L8, L9, L10, L11, L12;

[Netlist/Delay Format]

[IO Types]
layer = OFF;
CK = LVCMOS18, PIN, 0, -;
F4 = LVCMOS18, PIN, 0, -;
F3 = LVCMOS18, PIN, 0, -;
F2 = LVCMOS18, PIN, 0, -;
F1 = LVCMOS18, PIN, 0, -;
F0 = LVCMOS18, PIN, 0, -;
SHDN = LVCMOS33, PIN, 1, -;
TP1 = LVCMOS18, PIN, 0, -;
TP2 = LVCMOS18, PIN, 0, -;
TP3 = LVCMOS18, PIN, 0, -;
CONV = LVCMOS33, PIN, 1, -;
SDO = LVCMOS33, PIN, 1, -;
SCK = LVCMOS33, PIN, 1, -;
SDI = LVCMOS33, PIN, 1, -;
L0 = LVCMOS18, PIN, 0, -;
L1 = LVCMOS18, PIN, 0, -;
L2 = LVCMOS18, PIN, 0, -;
L3 = LVCMOS18, PIN, 0, -;
L4 = LVCMOS33, PIN, 1, -;
L5 = LVCMOS33, PIN, 1, -;
L6 = LVCMOS33, PIN, 1, -;
L7 = LVCMOS18, PIN, 0, -;
L8 = LVCMOS18, PIN, 0, -;
L9 = LVCMOS18, PIN, 0, -;
L10 = LVCMOS18, PIN, 0, -;
L11 = LVCMOS33, PIN, 1, -;
L12 = LVCMOS33, PIN, 1, -;

[Pullup]
HOLD = CK, F4, F3, F2, F1, F0, SHDN, TP1, TP2, TP3, CONV, SDO, SCK, SDI, L0, L1, 
	L2, L3, L4, L5, L6, L7, L8, L9, L10, L11, L12;

[Slewrate]
SLOW = F4, F3, F2, F1, F0, SHDN, TP1, TP2, TP3, CONV, SCK, SDI;

[Region]

[Timing Constraints]
layer = OFF;

[HSI Attributes]

[Input Delay]

[Pin attributes list]

[Attributes list setting]

[Power Guard]

[opt global constraints list]

[Explorer User Settings]

[LOCATION ASSIGNMENTS LIST]

[RESOURCE RESERVATIONS LIST]

[individual constraints list]

[Timing Analyzer]

[ORP Bypass]

[PLL Assignments]

[Register Powerup]
RESET = F4, F3, F2, F1, F0, SHDN, TP1, TP2, TP3, CONV, SCK, SDI;

[global constraints list]

[Global Constraints Process Update]

[Explorer Results]

[VHDL synplify constraints]

[VHDL spectrum constraints]

[verilog synplify constraints]

[verilog spectrum constraints]

[VHDL synplify constraints list]

[VHDL spectrum constraints list]

[verilog synplify constraints list]

[verilog spectrum constraints list]

[Constraint Version]
version = 1.0;

[ORP ASSIGNMENTS]
layer = OFF;

[Node attribute]
layer = OFF;

[SYMBOL/MODULE attribute]
layer = OFF;

[Nodal Constraints]
layer = OFF;

[OSCTIMER Assignments]
layer = OFF;