library ieee;  
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity main is
	port (RCK, RP : in std_logic; 
		OND, ENL, ONL : out std_logic;
		TP1, TP2 : out std_logic);
end;

architecture behavior of main is
	constant OnEnd : integer := 32767;
begin

	OnTimer: process is
		variable counter : integer range 0 to OnEnd := 0;
	begin
		wait until (RCK = '1');
		if (RP = '1') then 
			counter := 0;
			OND <= '1';
		else
			if (counter = OnEnd) then 
				counter := OnEnd;
				OND <= '0';
			else 
				counter := counter + 1;
				OND <= '1'; 
			end if;
		end if;
  end process;
  
  ENL <= '1';
  ONL <= RP;
  TP1 <= RCK;
  TP2 <= RP;
end;