library ieee;  
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity main is
	port (RCK, RP : in std_logic; 
		OND, ENL, ONL : out std_logic;
		TP1, TP2 : out std_logic);
end;

architecture behavior of main is
	constant OnEnd : integer := 511;
	constant PowerupEnd : integer := 31;
	component OSCH is 
		port (STDBY: IN  std_logic; OSC: OUT std_logic; SEDSTDBY: OUT std_logic);
	end component;
	signal BGOFF, BGCLR, OSCOFF, CK: std_logic;
begin
	OSCHInst0: OSCH port map (STDBY => OSCOFF, OSC => CK);
	PCNTRInst0: entity Power_Controller port map (USERSTDBY => BGOFF, CLRFLAG => BGCLR);
	
	Powerup: process is
		variable a : integer range 0 to PowerupEnd := 0;
	begin
		wait until (RCK = '1');
		if (a = PowerupEnd) then 
			a := a;
			OSCOFF <= '1';
			BGOFF <= '1';
			BGCLR <= '0';
		else
			a := a + 1;
			OSCOFF <= '0';
			BGOFF <= '0';
			if (a = PowerupEnd-1) then BGCLR <= '1'; else BGCLR <= '0'; end if;
		end if;
	end process;

	OnTimer: process is
		variable counter : integer range 0 to OnEnd := 0;
	begin
		wait until (RCK = '1');
		if (RP = '1') then 
			counter := 0;
			OND <= '1';
		else
			if (counter = OnEnd) then 
				counter := OnEnd;
				OND <= '0';
			else 
				counter := counter + 1;
				OND <= '1'; 
			end if;
		end if;
	end process;
  
  TP1 <= CK;
  TP2 <= BGCLR;
  ENL <= '0';
  ONL <= '0';
 end;