library ieee;  
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity main is
	port (RCK, RP : in std_logic; 
		OND, ENL, ONL : out std_logic;
		CKIN2 : in std_logic;
		CKOUT2: out std_logic;
		TP1, TP2 : out std_logic);
end;

architecture behavior of main is

	signal USERSTDBY, CLRFLAG, STDBY: std_logic;

begin

	PCNTRInst0: entity Power_Controller port map (USERSTDBY => USERSTDBY, CLRFLAG => CLRFLAG, STDBY => STDBY);
	PowerUp: process is
		constant PowerUpEnd : integer := 3;
		variable counter : integer range 0 to PowerUpEnd := 0;
	begin
		wait until (RCK = '1');
		if (counter = PowerUpEnd) then 
			counter := counter;
			USERSTDBY <= '1';
			CLRFLAG <= '0';
		else
			counter := counter + 1;
			USERSTDBY <= '0';
			if (counter = PowerUpEnd-1) then CLRFLAG <= '1'; else CLRFLAG <= '0'; end if;
		end if;
	end process;

	PowerOff: process is
		constant PowerOffEnd : integer := 511;
		variable counter : integer range 0 to PowerOffEnd := 0;
	begin
		wait until (RCK = '1');
		if (RP = '1') then 
			counter := 0;
			OND <= '1';
		else
			if (counter = PowerOffEnd) then 
				counter := counter;
				OND <= '0';
			else 
				counter := counter + 1;
				OND <= '1'; 
			end if;
		end if;
	end process;
	
	CKOUT2 <= not CKIN2;
  
	TP1 <= USERSTDBY;
	TP2 <= STDBY;
	ENL <= '0';
	ONL <= '0';
end;