library ieee;  
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity main is
	port (RCK, RP : in std_logic; 
		OND, ENL, ONL : out std_logic;
		TP1, TP2 : out std_logic);
end;

architecture behavior of main is

	attribute syn_keep : boolean;
	attribute nomerge : string;
		
	signal USERSTDBY, CLRFLAG, STDBY : std_logic;
	attribute syn_keep of USERSTDBY, CLRFLAG, STDBY : signal is true;
	attribute nomerge of USERSTDBY, CLRFLAG, STDBY : signal is "";  

	component BUFBA is 
		port ( A:in std_logic; Z:out std_logic);
	end component;
	signal R1, R2, R3 : std_logic;
	attribute syn_keep of R1, R2, R3 : signal is true;
	attribute nomerge of R1, R2, R3 : signal is "";  

begin
	R1 <= RP and (not R3);
	del1 : BUFBA port map (R1,R2);
	del2 : BUFBA port map (R2,R3);

	Divider: process is
		variable counter: integer range 0 to 63;
	begin
		wait until (R1 = '1');
		if (counter = 63) then
			counter := 0;
		else 
			counter := counter + 1;
		end if;
		if (counter > 31) then
			TP2 <= '1';
		else
			TP2 <= '0';
		end if;
	end process;
	
	PCNTRInst0: entity Power_Controller port map (USERSTDBY => USERSTDBY, CLRFLAG => CLRFLAG, STDBY => STDBY);
	PowerUp: process is
		constant PowerUpEnd : integer := 3;
		variable counter : integer range 0 to PowerUpEnd := 0;
	begin
		wait until (RCK = '1');
		if (counter = PowerUpEnd) then 
			counter := counter;
			USERSTDBY <= '1';
			CLRFLAG <= '0';
		else
			counter := counter + 1;
			USERSTDBY <= '0';
			if (counter = PowerUpEnd-1) then CLRFLAG <= '1'; else CLRFLAG <= '0'; end if;
		end if;
	end process;
	TP1 <= STDBY;

	PowerOff: process is
		constant PowerOffEnd : integer := 511;
		variable counter : integer range 0 to PowerOffEnd := 0;
	begin
		wait until (RCK = '1');
		if (RP = '1') then 
			counter := 0;
			OND <= '1';
		else
			if (counter = PowerOffEnd) then 
				counter := counter;
				OND <= '0';
			else 
				counter := counter + 1;
				OND <= '1';
			end if;
		end if;
	end process;

	ENL <= '0';
	ONL <= '0';
end;