library ieee;  
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity main is
	port (RCK, RP : in std_logic; 
		OND, ENL, ONL : inout std_logic;
		TP1, TP2, TP3 : out std_logic);
end;

architecture behavior of main is
	attribute syn_keep : boolean;
	attribute nomerge : string;

-- Power Controller 		
	signal USERSTDBY, CLRFLAG, STDBY : std_logic;
-- Ring Oscillator
	component BUFBA is port ( A:in std_logic; Z:out std_logic); end component;
	signal R1, R2, R3 : std_logic;
	attribute syn_keep of R1, R2, R3 : signal is true;
	attribute nomerge of R1, R2, R3 : signal is "";  
-- Data Clock
	signal DCK : std_logic;
-- Command Receiver
	signal cmd : std_logic_vector(7 downto 0) := "00000000";
	signal crs : integer range 0 to 63 := 0;
	signal RXC, NCS, IC, TC : std_logic;
-- Command Interpreter
	signal ACT : std_logic;
begin

-- Standby Controller
	PCNTR_Inst0: entity Power_Controller port map (USERSTDBY => USERSTDBY, CLRFLAG => CLRFLAG, STDBY => STDBY);
	PowerUp: process is
		constant PowerUpEnd : integer := 3;
		variable counter : integer range 0 to PowerUpEnd := 0;
	begin
		wait until (RCK = '1');
		if (counter = PowerUpEnd) then 
			counter := counter;
			USERSTDBY <= '1';
			CLRFLAG <= '0';
		else
			counter := counter + 1;
			USERSTDBY <= '0';
			if (counter = PowerUpEnd-1) then 
				CLRFLAG <= '1'; 
			else 
				CLRFLAG <= '0'; 
			end if;
		end if;
	end process;

-- Power Switch
	OND <= ACT or RXC;

-- Transmit Initiation Detector
	Initiate_Pulse: process is 
		constant endcount : integer := 65;
		variable counter : integer range 0 to endcount := 0;
	begin
		wait until (RCK = '1');
		if (RP = '0') then 
			counter := 0;
			IC <=  '0';
		else
			if (counter = endcount) then 
				counter := endcount;
				IC <= '1';
			else 
				counter := counter + 1;
				IC <= '0';
			end if;
		end if;
	end process;
	
-- Transmit Termination Detector	
	Terminate_Pulse: process is 
		constant endcount : integer := 192;
		variable counter : integer range 0 to endcount := 0;
	begin
		wait until (RCK = '1');
		if (RP = '0') then 
			if (counter = endcount) then 
				counter := endcount;
				TC <= '1';
			else 
				counter := counter + 1;
				TC <= '0';
			end if;
		else
			counter := 0;
			TC <=  '0';
		end if;
	end process;
	
-- Command Receiver
	Receiver: process is
		constant endstate : integer := 63;
		variable next_crs : integer range 0 to endstate;
	begin
		wait until (RCK = '1');
		
		if (crs = 0) then
			if (IC = '1') then 
				crs <= crs + 1;
			else 
				crs <= crs;
			end if;
		end if;
		if (crs = 1) then
			if (RP = '0') then 
				crs <= crs + 1;
			else 
				crs <= crs;
			end if;
		end if;
		if (crs = 2) then
			if (TC = '1') then 
				crs <= endstate;
			else 
				if (RP = '0') then 
					crs <= crs;
				else 
					crs <= crs + 1;
				end if;
			end if;
		end if;
		if (crs >= 3) and (crs <= 40) then
			crs <= crs + 1;
		end if;
		if (crs = 41) then 
			if (RP = '1') then 
				crs <= 0;
			else 
				crs <= 2;
			end if;
		end if;
		if (crs > 41) and (crs < endstate) then
			crs <= 0;
		end if;
		if (crs = endstate) then 
			crs <= 0;
		end if;
		
		if (crs = 41) then
			NCS <= '1';
		else 
			NCS <= '0';
		end if;

		if (crs > 0) then
			RXC <= '1';
		else
			RXC <= '0';
		end if;
	end process;

-- Command Interpreter
	Interpret: process is
		variable c : integer range 0 to 255 := 0;
	begin
		wait until (NCS = '1');
		c := to_integer(unsigned(cmd));
		if (c = 0) then 
			ENL <= '0';
			ONL <= '0';
			ACT <= '0';
		end if;
		if (c = 1) then 
			ENL <= '1';
			ONL <= '0';
			ACT <= '1';
		end if;
		if (c = 2) then 
			ENL <= '1';
			ONL <= '1';
			ACT <= '1';
		end if;
		if (c >= 3) then 
			ENL <= ENL;
			ONL <= ENL;
			ACT <= ACT;
		end if;
	end process;

-- Ring Oscillator 
	R1 <= IC and (not R3);
	del1 : BUFBA port map (R1,R2);
	del2 : BUFBA port map (R2,R3);

-- Data Clock Source
	Data_Clock: process is
		variable counter: integer range 0 to 63 := 0;
	begin
		wait until (R1 = '1');
		if (counter = 63) then
			counter := 0;
		else 
			counter := counter + 1;
		end if;
		if (counter > 31) then
			DCK <= '1';
		else
			DCK <= '0';
		end if;
	end process;

-- Lamp Control
	TP1 <= NCS;
	TP2 <= RXC;
	TP3 <= STDBY or DCK;
end;