[Device]
Family = lc4k;
PartNumber = LC4064ZC-75M56C;
Package = 56csBGA;
PartType = LC4064ZC;
Speed = -7.5;
Operating_condition = COM;
Status = Production;
EN_PinGLB = yes;
EN_PinMacrocell = yes;

[Revision]
Parent = lc4k64c.lci;
DATE = 04/24/2023;
TIME = 12:12:30;
Source_Format = ABEL_Schematic;
Synthesis = Synplify;

[Ignore Assignments]

[Clear Assignments]

[Backannotate Assignments]

[Global Constraints]

[Location Assignments]
layer = OFF;
CK = pin,A2,-,-,-;
F4 = pin,A7,-,-,-;
F3 = pin,D10,-,-,-;
F2 = pin,G10,-,-,-;
F1 = pin,K10,-,-,-;
F0 = pin,K9,-,-,-;
SHDN = pin,K5,-,-,-;
TP1 = pin,C1,-,-,-;
TP2 = pin,D1,-,-,-;
TP3 = pin,G1,-,-,-;
CSS = pin,C10,-,-,-;
CST = pin,K8,-,-,-;
SDO = pin,E10,-,-,-;
SCK = pin,H10,-,-,-;
A0 = pin,A1,-,-,-;
A1 = pin,H1,-,-,-;
L0 = pin,C7,-,-,-;
L1 = pin,H4,-,-,-;
KP = pin,F1,-,-,-;

[Group Assignments]
layer = OFF;

[Resource Reservations]
layer = OFF;

[Fitter Report Format]

[Power]

[Source Constraint Option]

[Fast Bypass]

[OSM Bypass]

[Input Registers]

[Netlist/Delay Format]

[IO Types]
layer = OFF;
F4 = LVCMOS18, PIN, 1, -;
F3 = LVCMOS18, PIN, 1, -;
F2 = LVCMOS18, PIN, 1, -;
F1 = LVCMOS18, PIN, 1, -;
F0 = LVCMOS18, PIN, 1, -;
SHDN = LVCMOS18, PIN, 0, -;
TP1 = LVCMOS18, PIN, 0, -;
TP2 = LVCMOS18, PIN, 0, -;
SCK = LVCMOS18, PIN, 1, -;
CSS = LVCMOS18, PIN, 1, -;
CST = LVCMOS18, PIN, 1, -;
A0 = LVCMOS18, PIN, 0, -;
A1 = LVCMOS18, PIN, 0, -;
CK = LVCMOS18, PIN, 0, -;
TP3 = LVCMOS18, PIN, 0, -;
SDO = LVCMOS18, PIN, 1, -;
L0 = LVCMOS18, PIN, 1, -;
L1 = LVCMOS18, PIN, 0, -;
KP = LVCMOS18, PIN, 0, -;

[Pullup]
Default = HOLD;

[Slewrate]
SLOW = F4, F3, F2, F1, F0, SHDN, TP1, TP2, SCK, CSS, CST, A0, A1, TP3, KP;

[Region]

[Timing Constraints]
layer = OFF;

[HSI Attributes]

[Input Delay]

[opt global constraints list]

[Explorer User Settings]

[Pin attributes list]

[global constraints list]

[Global Constraints Process Update]

[pin lock limitation]

[LOCATION ASSIGNMENTS LIST]

[RESOURCE RESERVATIONS LIST]

[individual constraints list]

[Attributes list setting]

[Timing Analyzer]

[PLL Assignments]

[Dual Function Macrocell]

[Explorer Results]

[VHDL synplify constraints]

[VHDL spectrum constraints]

[verilog synplify constraints]

[verilog spectrum constraints]

[VHDL synplify constraints list]

[VHDL spectrum constraints list]

[verilog synplify constraints list]

[verilog spectrum constraints list]

[ORP Bypass]

[Register Powerup]

[Constraint Version]
version = 1.0;

[ORP ASSIGNMENTS]
layer = OFF;

[Node attribute]
layer = OFF;

[SYMBOL/MODULE attribute]
layer = OFF;

[Nodal Constraints]
layer = OFF;