"<pre>
MODULE P3047

TITLE 'P3047A'

"For A3047 assemblies such as the A3047BV1, equipped with LC4064ZC logic chip in
"BGA-56 package.

"Version 1.1 [02-MAR-23] Based upon P3028C03, this firmware is for the new A3047AV1
"assembly, schematic S3047A. Eliminate uniform sampling. Set up sixteen-state sample 
"selector. Implement fourteen-bit ADC readout, add TSEL and SSEL. Implement null 
"samples that do no readout or sample or transmission. Re-work comments, eliminating
"quotes at end of lines. Construct new version number table. Ship two samples with
"a bug in this version that causes feedthrough crosstalk between one channel and 
"the next, fix this bug and freeze this version.

"Version 2.1 [19-JUL-23] Notice that sampling is not regular when we do not convert
"in one of the sample counter states. The V1 generates 64 Hz noise in CH0 and CH2
"because we are transmitting 960 SPS and our transmit state machine runs at 
"1024 SPS. We increase the temperature sample rate to 128 SPS and the noise dis-
"appears. From this we conclude that no sample instant may be unused in the cycle.
"Allow more time for ADC input to settle after switching channels. Add CSS pulse at 
"end of sample period so as the make sampling uniform. Synchronize CSS with TCK.
"We are now sampling before readout, so we select the same channel we are about to
"read out.

"Version 3.1 [28-SEP-23] Specify CC directly with an ID constant and set number
"rather than using intermedicate ID variable. We found this made the A3049 code
"more stable, so transferring it here. Fix faulty scheme for managing self-
"calibration and readout of thermometer ADC. We introduce CAL flag that is 
"set on power-up. Output pins on this chip can be set or cleared on power-up,
"but not other nodes. So we dedicate an unused pin for CAL. We clear CAL after
"the first ADC readout. During this first readout, we deliver 24 falling edges
"on SCK to the thermometer ADC. At all other times we deliver 18 falling edges.
"By this means, we have self-calibrating ADC on start-up and we eliminate what
"we called ADC Interference Noise.

"Version 4.1 [12-SEP-24] Add Version 3, four-input transmitter with temperature.

"Version 5.1 [21-OCT-24] Add Version 4, four-input 256 SPS no temperature.

"Version 6.1 [29-NOV-24] Change eck_offset to xck_offset, replace ECK with XCK. 
"Reduce xck_offset values to minimize noise. Reintroduce ECK as final CK period 
"in each sample interval. Replace CK with ECK in test points to minimize noise
"transmission.

"Version 6.2 [23-DEC-24] Remove ADC1..ADC3, saving three outputs.

declarations


"Configuration Parameters
"========================

" -----------------------------------------
"| Version |        Sample Rates (SPS)     |
"|         |-------------------------------|
"| Number  |  X1  |  X2  | X3  | X4  |  T  |
"|-----------------------------------------|
"|   1     |    0 | 256  | 128 | 512 | 128 |
"|   2     |  512 | 512  | 512 | 512 |   0 |
"|   3     |  128 | 256  |  64 | 512 |  64 |
"|   4     |  256 | 256  | 256 | 256 |   0 |
"|         |      |      |     |     |     |
" -----------------------------------------

"Set the transmitter version number

VERSION = 4;

"The base channel number is the channel number of the first transmit signal
"If only X is enabled, it is the X channel number. If only y is enabled, it
"is the Y channel number. If both are enabled, X is the base number and Y is
"the base number plus one. The base channel number can be 1-14, 17-30, 33-46,
"49-62, 65-78, 81-94, 97-110, 113-126, 129-142, 145-158, 161-174, 177-190,
"193-206, 209-222. These ranges correspond to sets 0-13 respectively,

base_channel_num = 5;

"The set number is the channel number divided by sixteen.

set_num = base_channel_num / 16;

"The base identifier is the channel number modulo sixteen.

base_id = base_channel_num % 16;


"Calibration Parameters
"======================

"Fast Clock Divisor, use to set TCK period in range 195-215 ns. Supported
"range for fck_divisor is 8 to 30.

fck_divisor = 30; 

"Frequency Low, use to center transmit spectrum in range 913-918 MHz.

frequency_low = 23;


"Parameters" 
"==========

"Set the transmit clock divisor, tck_divisor, and the ring oscillator length,
"ring_length, to suit fck_divisor. The TCK period will be two gate delays
"multiplied by tck_divisor multiplied by ring_length. For 7.5-ns chips, two
"internal gate delays are roughly 9.3 ns. The ring length must be at least 3.
"A ring length of 2 runs too fast, causing glitches and counter failure.
"The maximum ring length in this code is 13, but ultimately is limited by the
"available logic outputs. The tck_divisor must be 2 or greater. We need at least
"two divider states to create a symmetric transmit clock signal. And tck_divisor
"must also be less than 32 because we have at most five divisor bits in this
"code. As a result of these restrictions, some fck_divisor values do not have
"their own unique and correct combination of tck_divisor * ring_length. These are
"values 11, 13, 17, 19, 23, 29, 31, and 34.

@IF (fck_divisor == 8)  {tck_divisor = 2; ring_length = 4;}
@IF (fck_divisor == 9)  {tck_divisor = 3; ring_length = 3;}
@IF (fck_divisor == 10) {tck_divisor = 2; ring_length = 5;}
@IF (fck_divisor == 11) {tck_divisor = 2; ring_length = 5;}
@IF (fck_divisor == 12) {tck_divisor = 4; ring_length = 3;}
@IF (fck_divisor == 13) {tck_divisor = 4; ring_length = 3;}
@IF (fck_divisor == 14) {tck_divisor = 2; ring_length = 7;}
@IF (fck_divisor == 15) {tck_divisor = 5; ring_length = 3;}
@IF (fck_divisor == 16) {tck_divisor = 4; ring_length = 4;}
@IF (fck_divisor == 17) {tck_divisor = 4; ring_length = 4;}
@IF (fck_divisor == 18) {tck_divisor = 6; ring_length = 3;}
@IF (fck_divisor == 19) {tck_divisor = 6; ring_length = 3;}
@IF (fck_divisor == 20) {tck_divisor = 5; ring_length = 4;}
@IF (fck_divisor == 21) {tck_divisor = 7; ring_length = 3;}
@IF (fck_divisor == 22) {tck_divisor = 2; ring_length = 11;}
@IF (fck_divisor == 23) {tck_divisor = 8; ring_length = 3;}
@IF (fck_divisor == 24) {tck_divisor = 8; ring_length = 3;}
@IF (fck_divisor == 25) {tck_divisor = 5; ring_length = 5;}
@IF (fck_divisor == 26) {tck_divisor = 2; ring_length = 13;}
@IF (fck_divisor == 27) {tck_divisor = 9; ring_length = 3;}
@IF (fck_divisor == 28) {tck_divisor = 7; ring_length = 4;}
@IF (fck_divisor == 29) {tck_divisor = 7; ring_length = 4;}
@IF (fck_divisor == 30) {tck_divisor = 6; ring_length = 5;}
@IF (fck_divisor == 31) {tck_divisor = 6; ring_length = 5;}
@IF (fck_divisor == 32) {tck_divisor = 8; ring_length = 4;}
@IF (fck_divisor == 33) {tck_divisor = 11; ring_length = 3;}
@IF (fck_divisor == 34) {tck_divisor = 11; ring_length = 3;}
@IF (fck_divisor == 35) {tck_divisor = 7; ring_length = 5;}
@IF (fck_divisor == 36) {tck_divisor = 9; ring_length = 4;}

"Other Parameters

frequency_step=2;  "HI frequency - LO frequency
enable_rf=1;  "Enables RF oscillator, for testing.

"Channel ID

I3..I0 node istype 'com'; "Transmitter ID nodes
id = [I3..I0];

"Completion Code

CC3..CC0 node istype 'com'; "Completion Code Bits
cc =[CC3..CC0];


"Inputs and Outputs
"==================

CK pin A2; "Clock From 32-kHz Oscillator
F4..F0 pin A7,D10,G10,K10,K9 istype 'reg'; "DAC for frequency
!SHDN pin K5 istype 'com'; "Shutdown Control for Transmitter
TP1..TP3 pin C1, D1, G1 istype 'com'; "Test Point
!CSS pin C10 istype 'com'; "Chip Select for Signals ADC
!CST pin K8 istype 'reg'; "Chip select for Temperature ADC
SDO pin E10; "Serial Data Out for ADC
SCK pin H10 istype 'com'; "Serial Clock for ADC
A0..A1 pin A1,H1 istype 'com'; "Multiplexer Address
L0..L1 pin C7,H4; "Layout Pins
CAL pin F1 istype 'reg'; "Calibrate Flag, Set on Power-Up

"Nodes
"=====

FCK node istype 'com,keep'; "Fast Clock
TCK node istype 'reg,keep'; "Transmission Clock
ECK node istype 'reg,keep'; "End Clock
XCK node istype 'reg,keep'; "Channel Select Clock
VCK node istype 'reg,keep'; "VCO Clock
ST0..ST8 node istype 'reg'; "Sample Timer
SCNT0..SCNT3 node istype 'reg'; "Sample Counter
R1..R12 node istype 'com,keep'; "Ring Oscillator Bit
TXS0..TXS5 node istype 'reg,pos'; "Transmitter State
ACTIVE node istype 'reg,keep'; "Active period of 32-kHz
TXD node istype 'com,keep'; "Transmitter Done
TCKD0..TCKD4 node istype 'reg'; "Transmit Clock Divider
TCKDZ node istype 'reg,keep'; "Transmit Clock Divider Zero
ADC0 node istype 'reg'; "Least Significant ADC Bit
TTS0..TTS3 node istype 'reg'; "Transmit Time Shift
SDOS node istype 'reg,keep'; "SDO Synchronized
BIT node istype 'com,keep'; "The output bit value
SSEL node istype 'com'; "Signal Select, Not Temperature
RDS node istype 'reg'; "Read Sample"


"Sets
"====

"Set the clock divisor.

@IF (VERSION == 1) {
  ck_divisor=32; "Total Sample Rate 1024 SPS
  scnt = [SCNT3..SCNT0];
}
@IF (VERSION == 2) {
  ck_divisor=16; "Total Sample Rate 2048 SPS
  scnt = [SCNT1..SCNT0];
}
@IF (VERSION == 3) {
  ck_divisor=32; "Total Sample Rate 1024 SPS
  scnt = [SCNT3..SCNT0];
}
@IF (VERSION == 4){
  ck_divisor=32; "Total Sample Rate 1024 SPS
  scnt = [SCNT1..SCNT0];
}

"Sample Timer, depends upon ck_divisor to eliminate unused bits.
"Likewise, the active time, which is the moment during the period
"at which we transmit a sample, depends upon how many bits we have
"in the Sample Timer.

@IF (ck_divisor == 4) {
  "Frequency 8192 SPS, scatter is +-1 ticks.
  st = [ST1..ST0];
  active_time = [0,TTS0];
  xck_offset = 1;
}
@IF (ck_divisor == 8) {
  "Frequency 4096 SPS, scatter is +-2 ticks.
  st = [ST2..ST0];
  active_time = [0,TTS1,TTS0];
  xck_offset = 3;
}
@IF (ck_divisor == 16) {
  "Frequency 2048 SPS, scatter is +-4 ticks.
  st = [ST3..ST0];
  active_time = [0,TTS2,TTS1,TTS0];
  xck_offset = 5;
}
@IF (ck_divisor == 32) {
  "Frequency 1024 SPS, scatter is +-8 ticks.
  st = [ST4..ST0];
  active_time = [0,TTS3,TTS2,TTS1,TTS0];
  xck_offset = 7;
}
@IF (ck_divisor == 64) {
  "Frequency 512 SPS, scatter is +-8 ticks.
  st = [ST5..ST0];
  active_time = [0,0,TTS3,TTS2,TTS1,TTS0];
  xck_offset = 9;
}
@IF (ck_divisor == 128) {
  "Frequency 256 SPS, scatter is +-8 ticks.
  st = [ST6..ST0];
  active_time = [0,0,0,TTS3,TTS2,TTS1,TTS0];
  xck_offset = 11;
}
@IF (ck_divisor == 256) {
  "Frequency 128 SPS, scatter is +-8 ticks.
  st = [ST7..ST0];
  active_time = [0,0,0,0,TTS3,TTS2,TTS1,TTS0];
  xck_offset = 13;
}
@IF (ck_divisor == 512) {
  "Frequency 64 SPS, scatter is +-8 ticks.
  st = [ST8..ST0];
  active_time = [0,0,0,0,0,TTS3,TTS2,TTS1,TTS0];
  xck_offset = 15;
}

"Transmit Clock Divider, depends upon tck_divisor to eliminate unused
"bits

@IF (tck_divisor <= 4) {
  tckd = [TCKD1..TCKD0];
}
@IF (tck_divisor >= 5) & (tck_divisor <= 8) {
  tckd = [TCKD2..TCKD0];
}
@IF (tck_divisor >= 9) & (tck_divisor <= 16) {
  tckd = [TCKD3..TCKD0];
}
@IF (tck_divisor >= 17) {
  tckd = [TCKD4..TCKD0];
}

"Various Sets

txs = [TXS5..TXS0]; "Transmitter State
tts = [TTS3..TTS0]; "Transmit Time Shift
frequency = [F4..F0]; "Frequency Voltage for Five-Bit DAC
addr = [A1..A0];


"Readout and Transmit Constants
"==============================

num_sync_bits=11; "Number of synchronizing bits at transmission start.
num_id_bits = 4; "Number of ID bits
num_start_bits = 1; "Transmitted zero to mark data start
num_stop_bits = 4; "Not transmitted, for txs termination
num_data_bits = 16; "Number of ADC data bits
num_xmit_bits = "Number of transmission bit periods
    num_sync_bits
  + num_start_bits
  + num_id_bits
  + num_data_bits
  + num_id_bits; 
txs_done = "Final state of txs machine
    num_xmit_bits
  + num_stop_bits; 
first_sync_bit = 1;
first_start_bit = first_sync_bit + num_sync_bits;
first_id_bit = first_start_bit + num_start_bits;
first_data_bit = first_id_bit + num_id_bits;
first_cc_bit = first_data_bit + num_data_bits;
start_sck_sig = "The txs state for first SCK falling edge
    first_data_bit - 1;
end_sck_sig = "The txs state for last SCK falling edge
    start_sck_sig + num_data_bits - 1;
start_sck_T = "The txs state for first SCK falling edge
    first_data_bit - 2;
end_sck_T = "The txs state for last SCK falling edge
    start_sck_T + 17;
end_sck_T_cal = "The txs state for autocalibration, last SCK
    start_sck_T + 23;

"Table relating amplifier inputs to their multiplexer addresses.

x1_addr = 0;
x2_addr = 2;
x3_addr = 3;
x4_addr = 1;

"Version-dependent table of amplifier inputs to channel numbers.
@IF (VERSION == 1) {
  x2_id = base_id + 0;
  x3_id = base_id + 1;
  x4_id = base_id + 2; 
  T_id  = base_id + 3;
}
@IF (VERSION == 2) # (VERSION == 4) {
  x1_id = base_id + 0;
  x2_id = base_id + 1;
  x3_id = base_id + 2; 
  x4_id = base_id + 3;
}
@IF (VERSION == 3) {
  x1_id = base_id + 0;
  x2_id = base_id + 1;
  x3_id = base_id + 2; 
  x4_id = base_id + 3;
  T_id  = base_id + 4;
}


equations


"Sample Timing
"=============

"The Sample Timer runs off the 32.678-kHz clock and counts up to
"ck_divisor-1 to give a sample period of 32.768 kHz divided
"by ck_divisor.

st.clk=CK;
when (st==ck_divisor-1) then {
  st:=0;
} else {
  st:=st+1;
}

"The ECK clock marks the final CK period in each sample period.

ECK.clk=CK;
ECK:=(st==ck_divisor-1);

"The XCK clock marks the time when we switch from one input to
"another, which will be some time before we sample the input.

XCK.clk=CK;
XCK:=(st==ck_divisor-xck_offset-1);

"When ACTIVE is asserted, we begin a burst transmission.
"When it is unasserted, we reset the burst transmission
"state machine. We must make sure that ACTIVE remains true
"for long enough for the burst transmission to complete.
"The ACTIVE signal is true when the Sample Timer reaches 
"the active time set at the end of the previous sample period. 
"This active time is made up of the lower four bits of the 
"sample transmitted in the previous sample period. Because 
"these four bits are dominated by noise, they are random and so
"produce a random disturbance of the transmit instant, which
"avoids systematic collisions between transmitters. We transmit
"during every sample period, so we put no conditions upon 
"the ACTIVE signal other than that it occur some time in the
"sample period. We never try to save battery capacity by 
"skipping transmission because skipping introduces noise.

ACTIVE.clk=CK;
ACTIVE:=(st==active_time);

"TXD is true when the transmitter completes its burst
"transmission.

TXD=(txs==txs_done);


"Sample Selection
"================

"The Sample Counter counts sample periods and allows us to decide
"which input to digitize and which channel number to apply to each
"sample transmission. We increment the counter at the end of each
"sample period.

scnt.clk=XCK;
scnt:=scnt+1;

"Select one of the analog signals. For each value of scnt we
"set the id equal to the input selected on the previous value
"of scnt, since the ADC converts at the end of the readout.
"The mapping between addr and Xn is given by the x1_addr constants.

"Our channel selection uses a state machine with sixteen states.
"We pass from one state to another every time we get a rising
"edge on End Clock (ECK). In each state, we can either select
"the temperature sensor with TSEL, the signals with SSEL, or
"neither when both these are unasserted. If neither the ACTIVE
"signal will not be asserted. No ADC readout will take place, no
"conversion, and no RF transmission either. With TSEL the
"thermometer converter will be read out and a new conversion
"made after the readout. With SSEL, the previous signal ADC
"sample will be reat out and transmitted, followed by a new
"sample being taken. Each version of the code has its own 
"allocation for the sixteen sample states.

@IF (VERSION == 1) {
	when scnt==0 then  {id=x4_id; cc=15-x4_id+set_num; addr=x4_addr; SSEL=1;}
	when scnt==1 then  {id=x2_id; cc=15-x2_id+set_num; addr=x2_addr; SSEL=1;}
	when scnt==2 then  {id=x4_id; cc=15-x4_id+set_num; addr=x4_addr; SSEL=1;}
	when scnt==3 then  {id=x3_id; cc=15-x3_id+set_num; addr=x3_addr; SSEL=1;}
	when scnt==4 then  {id=x4_id; cc=15-x4_id+set_num; addr=x4_addr; SSEL=1;}
	when scnt==5 then  {id=x2_id; cc=15-x2_id+set_num; addr=x2_addr; SSEL=1;}
	when scnt==6 then  {id=x4_id; cc=15-x4_id+set_num; addr=x4_addr; SSEL=1;}
	when scnt==7 then  {id=T_id;  cc=15-T_id+set_num;  addr=x3_addr; SSEL=0;}
	when scnt==8 then  {id=x4_id; cc=15-x4_id+set_num; addr=x4_addr; SSEL=1;}
	when scnt==9 then  {id=x2_id; cc=15-x2_id+set_num; addr=x2_addr; SSEL=1;}
	when scnt==10 then {id=x4_id; cc=15-x4_id+set_num; addr=x4_addr; SSEL=1;}
	when scnt==11 then {id=x3_id; cc=15-x3_id+set_num; addr=x3_addr; SSEL=1;}
	when scnt==12 then {id=x4_id; cc=15-x4_id+set_num; addr=x4_addr; SSEL=1;}
	when scnt==13 then {id=x2_id; cc=15-x2_id+set_num; addr=x2_addr; SSEL=1;}
	when scnt==14 then {id=x4_id; cc=15-x4_id+set_num; addr=x4_addr; SSEL=1;}
	when scnt==15 then {id=T_id;  cc=15-T_id+set_num;  addr=x3_addr; SSEL=0;}
}

@IF (VERSION == 2) # (VERSION == 4) {
	when scnt==0 then  {id=x1_id; cc=15-x1_id+set_num; addr=x1_addr; SSEL=1;}
	when scnt==1 then  {id=x2_id; cc=15-x2_id+set_num; addr=x2_addr; SSEL=1;}
	when scnt==2 then  {id=x3_id; cc=15-x3_id+set_num; addr=x3_addr; SSEL=1;}
	when scnt==3 then  {id=x4_id; cc=15-x4_id+set_num; addr=x4_addr; SSEL=1;}
}

@IF (VERSION == 3) {
	when scnt==0 then  {id=x4_id; cc=15-x4_id+set_num; addr=x4_addr; SSEL=1;}
	when scnt==1 then  {id=x2_id; cc=15-x2_id+set_num; addr=x2_addr; SSEL=1;}
	when scnt==2 then  {id=x4_id; cc=15-x4_id+set_num; addr=x4_addr; SSEL=1;}
	when scnt==3 then  {id=x1_id; cc=15-x1_id+set_num; addr=x1_addr; SSEL=1;}
	when scnt==4 then  {id=x4_id; cc=15-x4_id+set_num; addr=x4_addr; SSEL=1;}
	when scnt==5 then  {id=x2_id; cc=15-x2_id+set_num; addr=x2_addr; SSEL=1;}
	when scnt==6 then  {id=x4_id; cc=15-x4_id+set_num; addr=x4_addr; SSEL=1;}
	when scnt==7 then  {id=x3_id; cc=15-x3_id+set_num; addr=x3_addr; SSEL=1;}
	when scnt==8 then  {id=x4_id; cc=15-x4_id+set_num; addr=x4_addr; SSEL=1;}
	when scnt==9 then  {id=x2_id; cc=15-x2_id+set_num; addr=x2_addr; SSEL=1;}
	when scnt==10 then {id=x4_id; cc=15-x4_id+set_num; addr=x4_addr; SSEL=1;}
	when scnt==11 then {id=x1_id; cc=15-x1_id+set_num; addr=x1_addr; SSEL=1;}
	when scnt==12 then {id=x4_id; cc=15-x4_id+set_num; addr=x4_addr; SSEL=1;}
	when scnt==13 then {id=x2_id; cc=15-x2_id+set_num; addr=x2_addr; SSEL=1;}
	when scnt==14 then {id=x4_id; cc=15-x4_id+set_num; addr=x4_addr; SSEL=1;}
	when scnt==15 then {id=T_id;  cc=15-T_id+set_num;  addr=x3_addr; SSEL=0;}
}


"Transmit Clock
"==============

"The ring oscillator turns on when ACTIVE and remains
"on until TXD. Each gate in the ring adds 2 ns to the
"delay around the ring. The period of the oscillation is
"4 ns multiplied by the number of gates.

@IF (ring_length == 2) {
  [FCK,R1]=[R1,!FCK & ACTIVE & !TXD];
}
@IF (ring_length == 3) {
  [FCK,R1..R2]=[R1..R2,!FCK & ACTIVE & !TXD];
}
@IF (ring_length == 4) {
  [FCK,R1..R3]=[R1..R3,!FCK & ACTIVE & !TXD];
}
@IF (ring_length == 5) {
  [FCK,R1..R4]=[R1..R4,!FCK & ACTIVE & !TXD];
}
@IF (ring_length == 6) {
  [FCK,R1..R5]=[R1..R5,!FCK & ACTIVE & !TXD];
}
@IF (ring_length == 7) {
  [FCK,R1..R6]=[R1..R6,!FCK & ACTIVE & !TXD];
}
@IF (ring_length == 8) {
  [FCK,R1..R7]=[R1..R7,!FCK & ACTIVE & !TXD];
}
@IF (ring_length == 9) {
  [FCK,R1..R8]=[R1..R8,!FCK & ACTIVE & !TXD];
}
@IF (ring_length == 10) {
  [FCK,R1..R9]=[R1..R9,!FCK & ACTIVE & !TXD];
}
@IF (ring_length == 11) {
  [FCK,R1..R10]=[R1..R10,!FCK & ACTIVE & !TXD];
}
@IF (ring_length == 12) {
  [FCK,R1..R11]=[R1..R11,!FCK & ACTIVE & !TXD];
}
@IF (ring_length == 13) {
  [FCK,R1..R12]=[R1..R12,!FCK & ACTIVE & !TXD];
}


"The transmit clock divider runs off FCK and divides FCK down
"to 5 MHz by correct choice of fck_divisor during transmitter
"calibration. We compute two constants from fck_divisor. One
"is tck_divisor, which sets the transmit clock period as a
"multiple of the fast clock period. The other is ring_length,
"which sets the number of gates in the ring oscillator that
"generates the fast clock. We enable the transmit clock divider
"only when the transmitter is active.

tckd.aclr=!ACTIVE;
tckd.clk=FCK;
when (tckd==tck_divisor-1) then {
  tckd:=0;
} else {
  tckd:=tckd+1;
}

"We detect the transmit clock divider being zero with TCKDZ. We
"clear TCKDZ to zero when the transmitter is inactive.

TCKDZ.aclr=!ACTIVE;
TCKDZ.clk=FCK;
TCKDZ:=(tckd==0);

"The transmit clock should be close to or a little less than 5 MHz,
"with a duty cycle of exactly 50%. Each time the transmit clock counts
"down to zero, we invert the transmit clock.

TCK.aclr=!ACTIVE;
TCK.clk=TCKDZ;
TCK:=!TCK;


"Transmission Control
"====================

"The transmitter state machine steps through all its
"states when ACTIVE is asserted, and then stops in its
"final state, waiting for !ACTIVE, which will reset the
"transmitter state to zero.

txs.aclr=!ACTIVE;
txs.clk=TCK;
when (txs==txs_done) then txs:=txs
else txs:=txs+1;

"Transmit synchronizing bits followed by four id bits, sixteen sample
"bits, and four completion code bits.

when (txs>0) & (txs<num_xmit_bits+1) then {
  when (
      (txs==0)&(1) "shutdown bit
    # (txs>=1)&(txs<first_start_bit) "sync bits
    # (txs==first_id_bit+0)&(I3) "id bit 3
    # (txs==first_id_bit+1)&(I2) "id bit 2
    # (txs==first_id_bit+2)&(I1) "id bit 1
    # (txs==first_id_bit+3)&(I0) "id bit 0
    # (txs>=first_data_bit)&(txs<first_cc_bit)&(SDOS) "ADC bits 15 down to 0
    # (txs==first_cc_bit+0)&(CC3) "cc bit 3
    # (txs==first_cc_bit+1)&(CC2) "cc bit 2
    # (txs==first_cc_bit+2)&(CC1) "cc bit 1
    # (txs==first_cc_bit+3)&(CC0) "cc bit 0
     ) then {BIT = 1} "transmit a 1
    else {BIT = 0} "transmit a 0
} else {BIT = 0} 

"We clock frequency with VCK, which we set up to give the
"bit value calculation time to settle after the rising edge
"of TCK. The VCK clock provides two pulses during each TCK
"period.

VCK.aclr=!ACTIVE;
VCK.clk=FCK;
VCK:=(tckd==1);

"The frequency DAC output is set by FHI and ACTIVE. When ACTIVE is not
"asserted, we set the DAC output to zero so as to stop current flowing
"into the DAC resistors.

frequency.aclr=!ACTIVE;
frequency.clk=VCK;
when TCK $ BIT then frequency := frequency_low + frequency_step
else frequency := frequency_low;

"Record the least significant ADC bit.

ADC0.clk=TCK;
when SSEL then {
  when (txs==end_sck_sig) then {
    ADC0 := SDOS;
  } else {
    ADC0 := ADC0;
  }
} else {
  when (txs==end_sck_T) then {
    ADC0 := SDOS;
  } else {
    ADC0 := ADC0;
  }
}

"We use a linear shift register to generate the random number
"we use to displace sample transmission, thus producing random
"transmit scatter. We feed the shift register with the least
"significant ADC bit, which will be randomized by input noise.

tts.clk=ECK;
TTS3 := ADC0 $ TTS0;
TTS2 := TTS3 $ TTS0;
TTS1 := TTS2;
TTS0 := TTS1;

"Shutdown (SHDN) turns off the RF transmitter.

when enable_rf then {
  SHDN=(txs==0)#TXD;
} else {
  SHDN=1;
}


"Conversion Control
"==================

"We calibrate our thermometer on power-up, for which we use an
"unused output pin for the calibration flag. Output pin registers
"can be set or cleared on power-up. We leave it set until we have
"performed one thermometer conversion.

CAL.clk = CK;
when CAL & !SSEL & ACTIVE then {
  CAL := 0;
} else {
  CAL := CAL;
}


"The !CSS input to the sixteen-bit ADC provokes conversion on 
"its rising edge and must be low during readout. We have one 
"uniformly-spaced pulse of length CK on CSS at the end of each 
"sample period, followed by another shorter pulse during the 
"ACTIVE period, subject to SSEL being asserted.

RDS.clk = TCK;
RDS := (txs>=start_sck_sig-2) & (txs<=end_sck_sig+1) & SSEL;
CSS = ECK # RDS;

"The !CST input to the fourteen-bit ADC acts in the same way 
"as !CSS, but we release CST a little earlier than we do CSS.
"We make sure we assert TSEL only when SSEL is not asserted.
"When CAL is set, as it will be on power-up, we assert CST
"for longer, to permit autocalibration.

CST.clk = TCK;
when !SSEL then {
  when CAL then {
    CST := (txs>=start_sck_T-2) & (txs<=end_sck_T_cal+1);
  } else {
    CST := (txs>=start_sck_T-2) & (txs<=end_sck_T+1);
  }
} else {
  CST := 0;
}

"We synchronize SDO with TCK.

SDOS.clk = TCK;
SDOS := SDO;

"We clock the ADC bits out of the chip as we transmit
"them, so we have no need for a register in which
"to save them.

when SSEL then {
  SCK = (txs>=start_sck_sig) & (txs<=end_sck_sig) & !TCK;
} else {
  when CAL then {
    SCK = (txs>=start_sck_T) & (txs<=end_sck_T_cal) & TCK;
  } else {
    SCK = (txs>=start_sck_T) & (txs<=end_sck_T) & TCK;    
  }
}


"Test Points
"===========

"The following test points allow us to calibrate the Transmit
"Clock (TCK), measure the exact sample rate (ECK pulse) and
"observe transmission scatter. We also include keeper inputs, 
"which are inputs through which we have routed power or ground.
"The CAL output is asserted only during power-up.

TP1 = (frequency==frequency_low+frequency_step);
TP2 = ECK & !L0 & !L1;
TP3 = CAL;


END