[Device] Family = lc4k; PartNumber = LC4064ZE-7MN64C; Package = 64csBGA; PartType = LC4064ZE; Speed = -7.5; Operating_condition = COM; Status = Production; EN_PinGLB = yes; EN_PinMacrocell = yes; [Revision] Parent = lc4k64e.lci; DATE = 05/09/2023; TIME = 13:18:56; Source_Format = ABEL_Schematic; Synthesis = Synplify; [Ignore Assignments] [Clear Assignments] [Backannotate Assignments] [Global Constraints] [Location Assignments] layer = OFF; CK = pin,E1,-,-,-; F4 = pin,F1,-,-,-; F3 = pin,D1,-,-,-; F2 = pin,C1,-,-,-; F1 = pin,B1,-,-,-; F0 = pin,A1,-,-,-; SHDN = pin,G8,-,-,-; TP1 = pin,H2,-,-,-; TP2 = pin,H3,-,-,-; LOUT = pin,H4,-,-,-; CSS = pin,A6,-,-,-; SDO = pin,A5,-,-,-; SCK = pin,A3,-,-,-; VL0 = pin,C4,-,-,-; VL1 = pin,E6,-,-,-; VL2 = pin,E7,-,-,-; VL3 = pin,E8,-,-,-; TDI = pin,A2,-,-,-; GND0 = pin,D2,-,-,-; GND1 = pin,D3,-,-,-; GND2 = pin,E2,-,-,-; GND3 = pin,F2,-,-,-; GND4 = pin,F5,-,-,-; GND5 = pin,G1,-,-,-; GND6 = pin,G2,-,-,-; GND7 = pin,G3,-,-,-; GND8 = pin,G4,-,-,-; GND9 = pin,G5,-,-,-; [Group Assignments] layer = OFF; [Resource Reservations] layer = OFF; [Fitter Report Format] [Power] [Source Constraint Option] [Fast Bypass] [OSM Bypass] [Input Registers] NONE = CK, SDO, VL0, VL1, VL2, VL3, GND0, GND1, GND2, GND3, GND4, GND5, GND6, GND7, GND8, GND9; [Netlist/Delay Format] [IO Types] layer = OFF; CK = LVCMOS18, PIN, 0, -; F4 = LVCMOS18, PIN, 0, -; F3 = LVCMOS18, PIN, 0, -; F2 = LVCMOS18, PIN, 0, -; F1 = LVCMOS18, PIN, 0, -; F0 = LVCMOS18, PIN, 0, -; SHDN = LVCMOS18, PIN, 1, -; TP1 = LVCMOS18, PIN, 0, -; TP2 = LVCMOS18, PIN, 0, -; LOUT = LVCMOS18, PIN, 0, -; SDO = LVCMOS18, PIN, 1, -; SCK = LVCMOS18, PIN, 0, -; VL0 = LVCMOS18, PIN, 0, -; VL1 = LVCMOS18, PIN, 1, -; VL2 = LVCMOS18, PIN, 1, -; VL3 = LVCMOS18, PIN, 1, -; GND0 = LVCMOS18, PIN, 0, -; GND1 = LVCMOS18, PIN, 0, -; GND2 = LVCMOS18, PIN, 0, -; GND3 = LVCMOS18, PIN, 0, -; GND4 = LVCMOS18, PIN, 1, -; GND5 = LVCMOS18, PIN, 0, -; GND6 = LVCMOS18, PIN, 0, -; GND7 = LVCMOS18, PIN, 0, -; GND8 = LVCMOS18, PIN, 0, -; GND9 = LVCMOS18, PIN, 1, -; CSS = LVCMOS18, PIN, 1, -; TDI = LVCMOS18, PIN, 0, -; [Pullup] HOLD = CK, F4, F3, F2, F1, F0, SHDN, TP1, TP2, LOUT, SDO, SCK, VL0, VL1, VL2, VL3, GND0, GND1, GND2, GND3, GND4, GND5, GND6, GND7, GND8, GND9, CSS, TDI; [Slewrate] SLOW = F4, F3, F2, F1, F0, SHDN, TP1, TP2, LOUT, SCK, CSS; [Region] [Timing Constraints] layer = OFF; [HSI Attributes] [Input Delay] [opt global constraints list] [Explorer User Settings] [Pin attributes list] [global constraints list] [Global Constraints Process Update] [pin lock limitation] [LOCATION ASSIGNMENTS LIST] [RESOURCE RESERVATIONS LIST] [individual constraints list] [Attributes list setting] [Timing Analyzer] [PLL Assignments] [Dual Function Macrocell] [Explorer Results] [VHDL synplify constraints] [VHDL spectrum constraints] [verilog synplify constraints] [verilog spectrum constraints] [VHDL synplify constraints list] [VHDL spectrum constraints list] [verilog synplify constraints list] [verilog spectrum constraints list] [Power Guard] [ORP Bypass] [Register Powerup] RESET = F4, F3, F2, F1, F0, SHDN, TP1, TP2, LOUT, SCK, CSS; [Constraint Version] version = 1.0; [ORP ASSIGNMENTS] layer = OFF; [Node attribute] layer = OFF; [SYMBOL/MODULE attribute] layer = OFF; [Nodal Constraints] layer = OFF; [OSCTIMER Assignments] layer = OFF;