[Device] Family = lc4k; PartNumber = LC4064ZC-75M56C; Package = 56csBGA; PartType = LC4064ZC; Speed = -7.5; Operating_condition = COM; Status = Production; EN_PinGLB = yes; EN_PinMacrocell = yes; [Revision] Parent = lc4k64c.lci; DATE = 05/26/2023; TIME = 14:17:33; Source_Format = ABEL_Schematic; Synthesis = Synplify; [Ignore Assignments] [Clear Assignments] [Backannotate Assignments] [Global Constraints] [Location Assignments] layer = OFF; CK = Pin, K9, -, -, -; F4 = Pin, A1, -, -, -; F3 = Pin, A3, -, -, -; F2 = Pin, A4, -, -, -; F1 = Pin, A6, -, -, -; F0 = Pin, A7, -, -, -; SHDN = Pin, A2, -, -, -; TP1 = Pin, F1, -, -, -; TP2 = Pin, G1, -, -, -; TP3 = Pin, H1, -, -, -; CSS = Pin, K4, -, -, -; SDO = Pin, K5, -, -, -; SCK = Pin, K7, -, -, -; SEL = Pin, E10, -, -, -; L0 = Pin, C10, -, -, -; L1 = Pin, B10, -, -, -; KP = Pin, D8, -, -, -; [Group Assignments] layer = OFF; [Resource Reservations] layer = OFF; [Fitter Report Format] [Power] [Source Constraint Option] [Fast Bypass] NONE = F4, F3, F2, F1, F0, SHDN, TP1, TP2, TP3, SCK, SEL, KP, CSS; [OSM Bypass] [Input Registers] NONE = CK, SDO, L0, L1; [Netlist/Delay Format] [IO Types] layer = OFF; F4 = LVCMOS18, PIN, 0, -; F3 = LVCMOS18, PIN, 0, -; F2 = LVCMOS18, PIN, 0, -; F1 = LVCMOS18, PIN, 1, -; F0 = LVCMOS18, PIN, 1, -; SHDN = LVCMOS18, PIN, 0, -; TP1 = LVCMOS18, PIN, 0, -; TP2 = LVCMOS18, PIN, 0, -; TP3 = LVCMOS18, PIN, 0, -; SCK = LVCMOS18, PIN, 1, -; SEL = LVCMOS18, PIN, 1, -; KP = LVCMOS18, PIN, 1, -; CK = LVCMOS18, PIN, 1, -; CSS = LVCMOS18, PIN, 0, -; SDO = LVCMOS18, PIN, 0, -; L0 = LVCMOS18, PIN, 1, -; L1 = LVCMOS18, PIN, 1, -; [Pullup] Default = HOLD; [Slewrate] SLOW = F4, F3, F2, F1, F0, SHDN, TP1, TP2, TP3, SCK, SEL, KP, CSS; [Region] [Timing Constraints] layer = OFF; [HSI Attributes] [Input Delay] [opt global constraints list] [Explorer User Settings] [Pin attributes list] [global constraints list] [Global Constraints Process Update] [pin lock limitation] [LOCATION ASSIGNMENTS LIST] [RESOURCE RESERVATIONS LIST] [individual constraints list] [Attributes list setting] [Timing Analyzer] [PLL Assignments] [Dual Function Macrocell] [Explorer Results] [VHDL synplify constraints] [VHDL spectrum constraints] [verilog synplify constraints] [verilog spectrum constraints] [VHDL synplify constraints list] [VHDL spectrum constraints list] [verilog synplify constraints list] [verilog spectrum constraints list] [ORP Bypass] NONE = F4, F3, F2, F1, F0, SHDN, TP1, TP2, TP3, SCK, SEL, KP, CSS; [Register Powerup] NONE = F4, F3, F2, F1, F0, SHDN, TP1, TP2, TP3, SCK, SEL, KP, CSS; [Constraint Version] version = 1.0; [ORP ASSIGNMENTS] layer = OFF; [Node attribute] layer = OFF; [SYMBOL/MODULE attribute] layer = OFF; [Nodal Constraints] layer = OFF;